1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Art
With the scale down of design rules, the miniaturization of memory elements is required. As a technology to break through the limit of highly integrating devices by miniaturization on a two-dimensional silicon substrate, a semiconductor memory device wherein memory elements are vertically (in a vertical direction to the surface of the substrate) disposed has been proposed. In such a vertical transistor, a source, a gate, and a drain are disposed in a vertical direction, and a body of amorphous silicon is formed between the source and the drain.
In such a vertical transistor, when a drain voltage is elevated, a depletion layer extends because the body is filled with amorphous silicon, the potential barrier where the inversion charge flowing from the end of the source into the channel impinges may lower, and the threshold value of the transistor may lower to deteriorate cutoff characteristics. Such a phenomenon is referred to as drain induced barrier lowering (DIBL).